1. The Field of the Invention
The present invention relates to a microprocessor which operates according to a computer program and a microcomputer that utilizes the microprocessor, in particular to a microprocessor that starts up to executes a periodic computer program which is defined as a computer program that starts up to be executed correctly at a predetermined time interval while the microprocessor executes a non-periodic computer program only if the periodic computer program is not running. In more particularly, the present invention relates to a starting up and stopping method for starting up and stopping to execute the periodic computer program when the non-periodic computer program is running and waiting for running, respectively.
2. Description of the Prior Art
Recently, conventional dedicated purpose computers or application specific circuits are permitted to be replaced with general purpose microprocessors (hereafter, referred to as “microprocessors” for simplicity) in accordance with the development of microcomputer technologies. One of advantages of the microcomputers can be attributed to a fact that a microcomputer that has a memory configured to execute predetermined operations defined by a computer program which is stored in the memory only after the microcomputer is activated. Thus, it is easily possible for a user to change operations which are needed to be carried out by the microcomputer for the user's convenience. In a use of the general purpose microcomputer, it is important to adjust the operation timing at which a predetermined operations defined by a computer program starts to be executed.
There is a known prior art method for adjusting the operation timings at which a periodic computer program should be started up to be executed repeatedly at a predetermined interval by the microprocessor. In the known method, while the microprocessor is already running a non-periodic computer program, an external timer circuit is connected to the microprocessor that has a central processing unit (CPU) and the external timer circuit outputs an interrupt instruction signal to the CPU of the microprocessor so as to stop or pause to run the non-periodic computer program. In more detail, the external timer circuit outputs the interrupt instruction signal periodically at a predetermined interval to the CPU of the microprocessor so as to generate a single highest level interrupt operation in processing of the microprocessor and to cause the microprocessor to start up running the periodic computer program instead of the non-periodic computer program periodically at the predetermined interval.
However, even though the microprocessor receives the highest level interrupt instruction signal, it sometimes occurs that an interrupt operation cannot be executed by the microprocessor immediately after receiving the highest level interrupt instruction signal. That is, for example, during a data transfer operation between memories which requires a plurality of bus cycles to carry out, during sequential operations defined by a branch instruction or during start-up and return sequential operations defined by another interrupt instruction than the single highest level interrupt instruction, any interrupt operation is prohibited to be executed until an operation among those mentioned above, that is, the data transfer operation, the sequential operations, and the like, will be completed even if some interrupt instruction signal is received by the microcomputer. In other words, when the microprocessor is executing one of the above mentioned operations, even if the microprocessor receives an interrupt instruction signal from the external timer circuit in order to start up periodic operations determined by the periodic computer program, the microprocessor cannot start to execute an operation defined by the interrupt instruction so that a start up timing when an execution of the periodic operations is started is delayed. Therefore, it is difficult for the microprocessor to start executing the periodic computer program precisely at the predetermined interval.
One conventional microprocessor for solving such the problem and for reliably starting to execute the periodic computer program at the predetermined interval is disclosed in Japanese Patent Laid-open No. Hei 5-233277. A microprocessor has a processing unit, a time adjustment unit, and a buffer. The processing unit executes an instruction code. The time adjustment unit adjusts the time between two instruction codes. All of the processing unit, the time adjustment unit, and the buffer share an internal bus, besides the buffer connects to an external bus. The time adjustment unit has a time measurement unit, a certain time set unit, a difference operation unit, and an idle state insertion unit. The time measuring unit measures the time between two instruction codes. The certain time set unit sets a certain time. The difference operation unit computes the difference between a time set by the certain time set unit and a further time measured by the time measuring unit. The idle state insertion unit inserts an idle state for a period corresponding to the difference obtained by the difference operation unit.
The microcomputer disclosed in Japanese Patent Laid-open No. Hei 5-233277 to Aihara and Hoshino is configured to start to execute a computer program at a predetermined time as follows.
If the processing unit executes a first instruction which indicates initiating a periodic operation defined by the periodic computer program, a counter value of the time measurement unit is initialized to 0. The counter value thereof is incremented at the predetermined interval. Here, it is assumed t1001 is a time when the first instruction is issued.
Then, the processing unit executes a second instruction which indicates finishing the periodic operation defined by the periodic computer program. Here, it is assumed t1002 is a time when the second instruction is issued. Next, the difference operation unit calculates the difference between the time set by the certain time set unit and the further time measured by the time measuring unit, that is, t1002-t1001, and outputs the difference t1002-t1001 to the idle state insertion unit. The idle state insertion unit pauses for executing any operation of the processing unit until the sum of the difference t1002-t1001 calculated by the difference operation unit and an idling period over which the idle state insertion unit outputs a necessary number of no operation (NOP) instructions becomes to be equal to a predetermined specific period, and then resumes its operation. It is assumed that the time when the processing unit resumes its operation is t1003 and the specific period is t1003-t1001.
By the operation described above, that is, by insertion of the suitable number of the idle states which fills a period between a time when the processing unit completes to execute some instruction and the certain time set by the certain time set unit, it is possible to adjust a time when a computer program is started to be execute by the processing unit. Therefore, it becomes possible to reliably start the periodic computer program by the microprocessor at the predetermined interval.
In more detail, the difference t1002-t1001 becomes smaller if the idling period from t1002 to t1003 becomes longer. In contrast, a shorter idling period from t1002 to t1003 results in a larger difference t1002-t1001. Even though an execution speed of the processing unit depends on a condition of the microprocessor such as an access delay generated in accessing a memory, frequency of a clock of the microprocessor, and the like, the specific period can be kept constant irrespective of the execution speed of the processing unit.
However, only adjustment of the specific period between two instructions is taken into consideration in the microprocessor disclosed in Japanese Patent Laid-open No. Hei 5-233277. That is, as to a method for changing the counter value of the time measurement unit according to an instruction defined by a computer program, only the disclosed method is one by which the counter value of the time measurement unit is set to 0 in response to execution of the first instruction which indicates initiating a periodic operation defined by the periodic computer program. Further, the case where the difference t1002-t1001 calculated by the difference operation unit attains a negative value, i.e., an elapsed period between the time t1001 set by the certain time set unit and the further time t1002 measured by the time measuring unit becomes unexpectedly long so as to exceed the specific period t1003-t1001, is not taken into consideration.
Another conventional real-time microprocessor directed to solve the above mentioned problems is disclosed in Japanese Patent Laid-open No. 2000-330785 corresponding to U.S. Pat. No. 7,069,425.
The real-time processor disclosed in Japanese Patent Laid-open No. 2000-330785 corresponding to U.S. Pat. No. 7,069,425 to Takahashi includes a clock register, a time register, a time comparator, and an instruction processing unit. The clock resister updates a time at a predetermined interval. The time register stores an arbitrary time. The instruction processing unit executes an instruction whose execution status depends on the comparison result obtained by the time comparator. The real-time processor constructed as above can carry out a predetermined operation correctly at a predetermined time irrespective of various factors, such as conditions of a memory and a timer both provided in the real-time processor. For example, the real-time processor of Takahashi can carry out any processing without overflow of the timer which measures the current time, and can detect failure of execution of a predetermined operation at a predetermined time and carry out a recovery procedure. In the real-time processor of Takahashi, the match or magnitude comparison between the value of the clock register and the value of the time register is carried out by the time comparator so as to judge what kind of the status among scheduling standby, scheduling establishment and scheduling violation the real-time microprocessor satisfies. The result of this judgment is used to execute a time dependent instruction by the instruction processing unit. The time dependent instruction includes a condition branch instruction, a memory reference instruction whose execution is temporally delayed, and a qualify instruction which is an instruction to be executed after the currently executing instruction is completed whose execution is temporally delayed.
However, both the microprocessor of Aihara and Hoshino and the real-time processor of Takahashi execute a suitable number of the NOP instruction, in order to start executing the periodic computer program at the predetermined interval. Therefore, the microprocessor and the real-time processor cannot exploit their computational resources.
The inventers of the present application considered that if the microprocessor executes the non-periodic computer program which does not need to start executing at a predetermined interval rather than the idling operation defined by the NOP instruction, it becomes possible to effectively utilize the computational resource of the microprocessor.
However, if it is intended that instead the microprocessor executes the idling operation defined by the NOP instruction the non-periodic computer program is run by the microprocessor, it is necessary that a synchronizing instruction which causes the microprocessor to synchronize two operations, i.e., one defined by a first computer program and a second one defined by the other computer program, have to be inserted into both the first and second computer programs. That is, if it is intended that the periodic computer program which needs to start running at a predetermined interval and the non-periodic computer program which is carried out while the periodic computer program is not processed are alternatively run by the microprocessor, the synchronizing instruction have to be inserted into both the periodic and non-periodic computer programs in order to synchronize the non-periodic operation with the periodic operation. This fact leads to make a development of the computer programs very complex since a programmer who writes the computer programs have to estimate the processing speed of the computer programs and to insert the synchronizing instruction to the computer programs at a suitable line in his development of the periodic and non-periodic computer programs.
Thus, if it is intended that the periodic computer program and the non-periodic computer program are alternatively run by the microprocessor, it can be considered that the microprocessor connects to the external timer circuit configured to outputs an interrupt instruction signal to the CPU of the microprocessor periodically at a predetermined interval in order to start executing the periodic computer program at a predetermined interval and to run the non-periodic computer program while the microprocessor is waiting to start executing the next periodic operation after completing the previous periodic operation.
However, as mentioned above with referring the technologies disclosed in Japanese Patent Laid-open No. Hei 5-233277 and in Japanese Patent Laid-open No. 2000-330785 corresponding to U.S. Pat. No. 7,069,425, the microprocessor cannot execute the interrupt operation directly in response to an input of the interrupt instruction from the external timer circuit according to the condition of the CPU of the microprocessor. As a result of this postponing of the interrupt operation, a delay in starting of the periodic operation is generated. Further, an accumulation of the delays generated at every starting timing results in not only a much delay in executing the periodic operation but also a cancellation of executing the periodic operation.